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On the Acceleration of Test Generation Algorithms

IEEE Transactions on Computers · 1983 · Vol. C-32(12) · pp. 1137–1144
FujiwaraShimono

Abstract

In order to accelerate an algorithm for test generation, it is necessary to reduce the number of backtracks in the algorithm and to shorten the process time between backtracks. In this paper, we consider several techniques to accelerate test generation and present a new test generation algorithm called FAN (fan-out-oriented test generation algorithm). It is shown that the FAN algorithm is faster and more efficient than the PODEM algorithm reported by Goel. We also present an automatic test generation system composed of the FAN algorithm and the concurrent fault simulation. Experimental results on large combinational circuits of up to 3000 gates demonstrate that the system performs test generation very fast and effectively.

VLSI and Analog Circuit TestingSoftware Testing and Debugging TechniquesIntegrated Circuits and Semiconductor Failure AnalysisAlgorithmComputer scienceAutomatic test pattern generationFault coverageGeneration timeCombinational logicElectronic circuitLogic gate
Citations
819
FWCI
11.93
field-weighted impact
References
12
Percentile
99%
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References
An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
IEEE Transactions on Computers · 1981 · 1,116 citations
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