Design and functional verification of 1*3 router using verilog

Abstract

The need for high-performance, low-latency, and energy-efficient routers has grown dramatically with the quick development of on-chip communication networks and System-on-Chip (SoC) designs. Routers play a crucial role in modern digital communication by efficiently directing data packets to their appropriate destinations. In order to ensure effective data packet transfer while reducing congestion and data loss, routers are essential. The design and verification of a 1x3 router using Verilog is presented in this work, with particular attention to the implementation of the Register-Transfer Level (RTL) and functional validation. To provide dependable and effective data transfer, the suggested router architecture incorporates essential elements such as a synchronization mechanism, First-In-First-Out (FIFO) buffers, and a control logic based on Finite State Machines (FSM). A comprehensive testbench framework in Vivado is used to verify its functionality, including assertions, coverage metrics, and guided and random test stimuli to guarantee accuracy.